DUE: Wednesday, March 18 @ 11:59:59 PM
By Tuesday, Feb 18, please make a post on Piazza with your project choice, along with your group members.
Final Project Guidelines
You can work in groups of up to 3, or individually. It is expected that projects involving 3 students will be of larger scope and greater difficulty than projects with 1 or 2 students. All students in the group will receive the same score.
A technical report is required. There are no formal page requirements. The report length should be as much as needed but not more. You must turn in your source code and detail how to compile and use your code base. Please indicate any dependencies or libraries you've used.
Project suggestions for group of 1
In Lab 1, we implemented simple forwarding and stalling logic into a 5 stage pipeline simulator. That simulator is purely a performance simulator to obtain timing. This project option is to extend this simulator to add some functionality. Specifically, you will be expected to extend and support:
- A working register file with 2 read ports and 1 write port. (Make the simulator functional.)
- Support for immediate instructions (ADDI and SUBI). It may be useful to include r0, which is hardwired to contain 0.
- We can utilize this to move data values into registers. For example, ADDI r1 r0 #5 moves the value 5 into r1.
- Support for conditional branches (BEQ and BNE)
- Since we do not have dynamic branch prediction, you can assume static branch prediction (always T or NT). Have a command-line parameter to specify the static predictor (always T or always NT).
- Assume we branch in ID stage and resolve the branch in EX stage.
- For branch offset, you can specify it in terms of instructions
- For example, BEQ r1 r2 5, you will compare if r1 == 2. If it is equal, you will branch and execute the 5th instruction after the BEQ instruction.
Project suggestions for group of 2
Tomasulo Simulator / Solver
For this project, you will be designing a configurable Tomasulo algorithm simulator.
This project will take in simple assembly instructions in a text file. Your simulator will then decode the instructions to drive the Tomasulo simulator. For simplicity, we can limit the ISA to the same instructions as in lab 1. Furthermore, we can limit the number of architectural registers to 10 (r0-r9).
You can assume we will have 1 of each: Memory Unit, Adder Unit, Mult/Div Unit, Branch Unit.
The following parameters must be configurable:
- Execution time of execution units (ex. Adder unit takes 2 cycles, Mult/Div Unit takes 20 cycles, etc.)
- Number of reservation stations for each execution unit resource
- Static branch predictor (Always T or Always NT)
- If taken, you can assume your branch will exit after 4 iterations
Simulator Output: Output in table form the solution for the Tomasulo Algorithm. Essentially, this is an automated homework solver. =)
Project suggestions for group of 3
There exist several well-established architecture competitions. They include simple simulators and benchmark traches where participants can compete and implement their own branch predictor, data prefetcher, or value predictor. A project for a group of 3 can "compete" in these competition by creating their own techniques. The goal is to design a technique that can improve upon a naive approach (For example, simple 2-bit branch predictor).
Data Prefetching Competition
Championship Value Prediction
Champtionship Branch Prediction
There is an open-ended project option. You can freely pick a project as long as the project is microarchitecture-related (optimizing applications for specific architectures do not count!). If you choose your own architecture project, please contact me first for approval.